1. Field of the Invention
The present invention generally relates to the field of computer systems, and more particularly, to an apparatus and method for accurately recording and regulating segment execution in processor architectures.
2. Background of the Related Art
Complex processor architectures are common elements in various computer systems such as input/output (I/O) systems, multiple function systems, and assorted subsystems thereof. These processor architectures generally include a primary central processing unit (CPU) 20, a memory controller 21, and a memory 22, as shown in FIG. 1. A processor bus 23 is generally used to interconnect CPU 20 and memory controller 21, a memory bus 24 is generally used to interconnect memory 22 and memory controller 21, and a system bus 25 is generally used to interconnect memory controller 21 to any additional devices in the architecture. In this configuration, memory controller 21 operates to regulate access to memory 22, both by CPU 20 and the additional devices in communication with the architecture via system bus 25. In regulating access to memory 22, memory controller 21 must also arbitrate between the devices requesting access to memory 22. Additionally, other base programming codes or software applications, often termed firmware, are used to execute the aforementioned regulation/arbitration functions, as well as to provide additional functionality. A building block of this firmware is an operating system, which is generally used to provide various CPU based functionality, depending upon the type of architecture, in addition to controlling access of segment execution to CPU 20 by additional firmware entities, wherein segment execution is generally defined as an instruction from a firmware entity to be executed by the processor. The operating system generally includes software-type instructions that may be stored in memory 22 that are generally executed in CPU 20.
As these complex processor architectures continue to develop, the need to accurately and efficiently measure and regulate firmware segment execution times within the processor architectures becomes critically important to effective operation of the architectures, as no single firmware entity should be allowed to monopolize execution time if the system as a whole is to cooperatively function in an efficient manner. To that end, various software based implementations for measuring and regulating segment execution times for processor architectures are currently available. These software based implementations generally calculate and update timestamps corresponding to the beginning and end of segment executions through the use of multiple software instructions executed by the operating system of the CPU. Thereafter, processor allocation to various firmware applications is regulated in accordance with the proportion of available processing time and the amount of segment processing time requested by the various firmware applications, such that over-utilization of a particular micro processor in a complex system by a single firmware entity can be avoided. As such, regulation of firmware allows for effective balancing and usage of the system processors from an overall system standpoint.
Although the various software based implementations are apparently able to calculate segment execution times in CPU 20 and regulate the subsequent processor allocation, the quantity of software instructions required by the software based processes themselves inherently results in a decreased efficiency of operation of the processing architecture as a whole. This is generally a result of the large quantity of firmware pathlength overhead necessary to record and regulate processor usage in a software based implementation, which itself contributes to the overhead usage and pathway congestion that the software is designed to reduce. In particular, current software based systems for monitoring and regulating CPU segment execution times utilize the CPU operating system to conduct the bulk of the monitoring and regulating operations. For example, current systems generally utilize the CPU operating system to execute a timestamp operation for monitoring segment execution times. In executing the timestamp operation through the CPU operating system, tens of clock cycles are often consumed, as the operating system must read a memory location having a start time value therein, add a delta time value to the start time value, and write the added value back out to a memory location.
Therefore, the software process itself contributes to the firmware pathlength overhead in the CPU operating system, as the operating system is tied up during the tens of clock cycles used for each timestamp operation corresponding to a segment execution. Taking into consideration that current processors may execute millions of segments per second, it follows that the current software based systems themselves substantially contribute to the overhead firmware pathlength that they are designed to minimize.
Therefore, there remains a need for a method and apparatus for monitoring and regulating segment execution times in a processing architecture, wherein the application itself does not significantly contribute to the firmware pathlength overhead of the CPU and/or operating system during operation.